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We accelerate wired connections
Ultra Low Latency IP
Patented Technology
Data rates of up to 112G serial
QuickLogic and eTopus Announce Disaggregated, Flexible eFPGA Chiplet Template
Press Release
Ultra Low Latency 400G IP
112G links are limited by FEC latency – as much as 100ns per link when driving a real world 30db+ channel
Our patented ultra low BER design – allows lowest latency 400G solution in the market
Our 400G LR IP solution delivers combined latency for FEC and SerDes of well under 10ns
Click here for more info
Technology Nodes
Wide range of nodes for SerDes IP
@ 6nm & 7nm up to 112G serial
@ 16 & 12 nm up to 56G serial
@ 22 nm up to 58G serial
Click here for more info
Protocols Supported
Wide range of protocols
Ethernet & Interlaken
Bunch of Wires
JESD & FC
LR PCIe Gen 5, CXL2.0/3 and Gen 6
Click here for more info
Coming Soon
Exciting new developments coming
Chiplets and higher speeds and new nodes
Join our mailing list to keep updated
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