ASIC Synthesis/STA Engineer
The eTopus team is comprised of industry experts in high-speed, mixed signal digital signal processing (DSP) communications systems. As an ASIC Synthesis/STA Engineer in eTopus, you will handle SoC/IP digital implementation for multi-million gate ultra-high speed networking devices, including synthesis, timing analysis and closure.
What can eTopus do for you?
- Potential for upward mobility in a fast-moving Silicon Valley startup
- Opportunity to work with the like-minded talent to solve challenging problems
- Becoming part of the creator of ultra-high speed interconnect technology to enable the next generation of Cloud Data Centers
What can you do for eTopus?
- Perform synthesis, timing constraints creation and static timing analysis for signoff
- Perform logic equivalence checking
- Refine UPF specifications for power analysis and perform estimations
- Perform SoC/IP PPA optimization and work closely with physical team for timing and design closure
Required skills and experience
- Logic Synthesis/Static-Timing-Analysis (STA) experience with exposure to Timing/Area/Power closure in leading edge technology
- Understanding of SystemVerilog, Verilog, and/or VHDL
- Intermediate to expert knowledge of Synthesis, STA, logic equivalence checking tools
- Experience with UPF/CPF specifications
- Scripting skills using TCL, Perl or shell
- Tape-out experience in 40nm / 28nm process nodes or below
- The ability to work independently and on a team while interfacing with team members located all over the world
Qualifications
- BS/MS/PhD in Electrical Engineering and Computer Engineering
Working Location
- Hong Kong office / Headquarters & Innovation Center