DFT Engineer
The eTopus team is comprised of industry experts in high-speed, mixed signal digital signal processing (DSP) communications systems. As a DFT Engineer in eTopus, you will handle all aspects of Design-For-Test(DFT) design for multi-million gate ultra-high speed networking devices.
What can eTopus do for you?
- Potential for upward mobility in a fast-moving Silicon Valley startup
- Opportunity to work with the like-minded talent to solve challenging problems
- Becoming part of the creator of ultra-high speed interconnect technology to enable the next generation of Cloud Data Centers
What can you do for eTopus?
- Participate in chip-level DFT architecture definition
- DFT Implementation in RTL/Netlist at block and SoC level as per specs for Memory BIST, LBIST, Boundary Scan, Scan and IP test
- ATPG patterns generation and simulation in RTL, netlist at block and SoC level
- Develop and validate DFT mode SDC constraints for Synthesis and STA
- Project flow setup and executing timing/non-timing simulations at block and SoC level
- Analyzing and improving scan coverage
- Perform logical equivalence checking
- Work closely with physical team throughout the development cycle
- Supporting failure analysis and debug
Required skills and experience
- Experience with the DFT integration at block and SoC level
- Experience in DFT methodology like scan test, boundary-scan, BIST and test access mechanisms
- Knowledge of Simulators, Synthesis, STA, logic equivalence checking tools
- Understanding of SystemVerilog, Verilog, and/or VHDL
- Scripting skills using TCL, Perl or shell
- The ability to work independently and on a team while interfacing with team members located all over the world
- Experience with Tessent is a plus
Qualifications
- BS/MS/PhD in Electrical Engineering and Computer Engineering
Working Location
- Hong Kong office / Headquarters & Innovation Center