Happy Thanksgiving! Share this post Recent Post Join us at Supercomputing 2022 in Dallas Read More Congratulations to eTopus Team Presenting at 2022 TSMC OIP Read More SerDes clocking catered to robust noise handling in advanced process technologies for HPC, Read More Load More
Join us at Supercomputing 2022 in Dallas Come and learn more about eTopus revolutionary UCIe ChipliPHY™️ products November 9, 2022 Superomputing 2022 – Our world is changing rapidly. Complex challenges are suddenly arising alongside an urgent demand for answers. Leveraging HPC, skilled minds employ innovative technologies to respond to the call — driven by data, …
Congratulations to eTopus Team Presenting at 2022 TSMC OIP October 27, 2022 Thanks TSMC for organizing a very successful 2022 TSMC OIP Forum for semiconductor innovators to see and share the latest development from the technology leaders. Our R&D team partnered with Siemens EDA team to highlight the experience of overcoming key design challenges …
Congratulations to eTopus Team Presenting at 2022 TSMC OIP Read More »
SerDes clocking catered to robust noise handling in advanced process technologies for HPC, Datacenter, 5G and AI applications Find out how eTopus aids high-speed data center links needed to support a wide span of data rates and protocols, employing complex modulation schemes and varying insertion loss requirements from VSR at few dBs to LR at …
Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet Applications to Achieve Compliance and High-Speed Connectivity Tewksbury, MA., June 21, 2022 Avery Design Systems, a leader in functional verification solutions, today announced it has been chosen by eTopus as its verification IP solution partner for eTopus PCIe Gen 1-6 …
QuickLogic and eTopus Announce Disaggregated, Flexible eFPGA Chiplet Template Targeting advanced, high-performance applications | Available initially as configurable IP and later as Known Good Die chiplets SAN JOSE, Calif., June 16, 2022 QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, and eTopus, a leader …
QuickLogic and eTopus Announce Disaggregated Flexible eFPGA Chiplet Template Read More »
Thank you for visiting us at DesignCon 2022 April 15, 2022 Thanks for visiting our booth and chatting with us at DesignCon 2022. Our team appreciated and enjoyed the opportunity to demo our PCIe and 112G Ethernet solution. Please checkout the press release regarding our demonstration of the Hirose mezzanine/card edge connectors and eTopus SerDes IP. …
Hirose and eTopus Technology Develop Combined PCIe Gen6 64Gbps PAM4 Interconnect Solution for AI Training Applications Complete bench setup using Hirose mezzanine/card edge connectors and eTopus SerDes IP will be demonstrated at DesignCon in San Jose San Jose, Calif. – April 6, 2022 Hirose Electric Co., Ltd., a global leader in connector technology, its design, …
eTopus Announces PCIe IP Gen 1-6 and 800G Support for 7/6nm with Support for SoC & Chiplet Clients San Jose, CA – Mar 29, 2022 eTopus Technology today announces the design-in availability of its 7/6nm multi-protocol SerDes IP optimized for PCIe Gen 1 to 6 SoC & Chiplet clients. This new IP also supports Ethernet …
eTopus Announces Collaborative IP Platform for Rapid and Economical Deployment of Chiplets Includes IPs such as SerDes, eFPGA, Ethernet MAC/PCS, Die2Die and RISC-V San Jose, CA – Feb 2, 2022 eTopus Technology today announced in partnership with QuickLogic and OpenFive, a platform of base IP that can be easily integrated by chiplet developers with minimal …