{"id":4587,"date":"2021-08-24T06:07:01","date_gmt":"2021-08-24T13:07:01","guid":{"rendered":"https:\/\/etopus.com\/?p=4587"},"modified":"2022-06-05T20:54:59","modified_gmt":"2022-06-06T03:54:59","slug":"etopus-selects-diakoptos-paragonx-platform-for-ultra-high-speed-serdes-ip","status":"publish","type":"post","link":"https:\/\/etopus.com\/zh\/etopus-selects-diakoptos-paragonx-platform-for-ultra-high-speed-serdes-ip\/","title":{"rendered":"eTopus Selects Diakopto\u2019s ParagonX\u2122 Platform for Ultra-High Speed SerDes IP"},"content":{"rendered":"
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eTopus Selects Diakopto\u2019s ParagonX\u2122 Platform for Ultra-High Speed SerDes IP<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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Breakthrough Software and Methodology Enables
\nFast and Insightful IC Design Debugging and Optimization<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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San Jose, CA \u2013 August 24, 2021<\/div>
\u00a0<\/div><\/div>

Diakopto announced today that eTopus, a pioneer of ultra-high speed ADC\/DSP-based SerDes for wireline applications, has chosen the ParagonX<\/a> platform and methodology for integrated circuits (IC) debugging and design improvement. ParagonX empowers eTopus engineers to quickly find the root causes of bottlenecks caused by layout parasitics, delivering actionable insights into how to fix and fully optimize their IC designs.<\/p>

eTopus designs ultra-high speed mixed-signal semiconductor solutions for high-performance computing and data center applications. Their ultra-high speed SerDes IP has been adopted by global Tier-1 players and is used in networking, storage, 5G, and AI applications. The company\u2019s ePHY\u2122 product line features a scalable system architecture that supports a wide range of data rates and wide range of insertion losses.<\/p>

\u201cWe have adopted ParagonX to speed up the development and tapeouts for multiple generations of our SerDes technology,\u201d said Harry Chan, CEO of eTopus. \u201cLayout parasitics have become one of the dominant problems in IC design. ParagonX stands alone in superior ease-of-use, analysis speed and in conveying insights that drive design improvements. \u00a0This has helped us develop higher quality and lower power SerDes IP at a much faster rate.\u201d<\/p>

Parasitics are unintended elements in IC designs that degrade a circuit\u2019s performance, precision, power efficiency, robustness, and reliability.\u00a0 The ever-increasing need for higher density, faster speed, and greater precision, coupled with continued migration to more advanced technology nodes have elevated their impact on IC design. The power-performance-area (PPA) metric and time-to-market of modern ICs are now dominated by on-chip interconnects and layout parasitics. Debugging these design problems \u2013 and addressing the underlying issues causing them – has become extraordinarily difficult, tedious, and time-consuming.<\/p>

ParagonX offers a new methodology that delivers insights to assist design, layout and CAD engineers to quickly and easily pinpoint bottlenecks and the sources of IC design problems caused by parasitics. It is orders of magnitude faster than other EDA solutions, and helps engineers quickly find the few critical parasitic elements (out of thousands, millions, or billions) responsible for bottlenecks, choke points and weak areas.<\/p>

\u201cWe are thrilled to count eTopus among the group of technology leaders embracing the ParagonX methodology and solution,\u201d commented Maxim Ershov, CEO and CTO of Diakopto. \u201cLayout parasitics are now ubiquitous and are especially challenging in ultra-high speed and high-performance designs. It is gratifying that ParagonX is enabling companies like eTopus to tackle these challenges.\u201d<\/p>

ParagonX offers superior ease-of-use and a unique out-of-the-box experience that enables novice users to get started with minimal training. The tool does not require complicated setup, configuration, CAD support, or foundry qualification. This highly intuitive and versatile methodology enables rapid adoption by new users and design teams. In addition, it improves the collaboration between IC design and layout engineers by providing a platform on which they can jointly analyze, visualize, debug and optimize parasitics-related issues.<\/p>

About Diakopto Inc.<\/strong><\/p>

Diakopto develops out-of-the-box analysis, visualization, and optimization tools for complex IC designs, with the primary focus on layout parasitics. We empower IC design, layout, and CAD engineers at over 30 industry-leading companies to quickly find and resolve design problems, increase productivity, and accelerate time-to-market. Our software platform and methodology are designed to deliver easy-to-use, intuitive, and fast functionalities, producing clear, visual, and actionable results. Diakopto is headquartered in San Jose, CA. www.diakopto.com<\/a><\/p>

About eTopus Technology Inc.<\/strong>
eTopus is an innovator and technology leader in high performance, DSP-based, mixed-signal, ultra-high-speed semiconductor interconnect solutions. Our ultra-high-speed SerDes IP is adopted by global Tier-1 players to be used in networking, storage, 5G, and AI applications. eTopus is a VC-backed startup headquartered in the center of Silicon Valley where our innovations and advanced architectures are developed. Multiple locations are set up globally in USA, Europe and Greater China to provide sales, design and customer support. www.etopus.com<\/a><\/p>

Diakopto and ParagonX are trademarks owned by Diakopto, Inc.<\/center>
All other trademarks are owned by their respective companies.<\/center><\/div>

Press Contacts:<\/strong><\/p>

Diakopto
<\/strong>Casey Jones
casey@diakopto.com<\/a>
+1 702 994 0605<\/p>

eTopus
<\/strong>Emily Au
emily.au@etopus.com<\/a>
+1 888 413 5488<\/p><\/div>

Reference: eTopus Selects Diakopto’s ParagonX\u2122 Platform for Ultra-High Speed SerDes IP (prnewswire.com)<\/a><\/p><\/div>

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