{"id":5306,"date":"2021-10-19T06:00:58","date_gmt":"2021-10-19T13:00:58","guid":{"rendered":"https:\/\/etopus.com\/?p=5306"},"modified":"2021-12-03T13:54:26","modified_gmt":"2021-12-03T21:54:26","slug":"etopus-introduces-400g4x100g-lr-ip-solution-incorporating-new-fec-ephy-with-combined-latency-of-sub-10ns","status":"publish","type":"post","link":"https:\/\/etopus.com\/zh\/etopus-introduces-400g4x100g-lr-ip-solution-incorporating-new-fec-ephy-with-combined-latency-of-sub-10ns\/","title":{"rendered":"eTopus introduces 400G(4x100G) LR IP solution incorporating new FEC & ePHY with combined latency of sub 10ns"},"content":{"rendered":"
\n\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t



eTopus introduces 400G(4x100G) LR IP solution incorporating new FEC & ePHY with combined latency of sub 10ns <\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\"\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t
<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t

San\u00a0Jose, CA \u2013\u00a0October 19, 2021\u00a0<\/span><\/p>

eTopus Technology, a pioneer of ultra-high-speed ADC\/DSP-based SerDes for wireline applications is proud to introduce its new 400G Long Range (LR) IP solution incorporating Forward Error Correction (FEC) IP and the eTopus DSP-based production-proven SerDes PHY (ePHY) IP with combined latency of sub 10ns.<\/span><\/p>

The solution has been silicon-proven in 6 and 7nm foundry processes and tested with multiple cable companies and is ready for volume production.<\/span><\/p>

The eTopus high-speed transceiver architecture supports a wide range of data rates for multiple standards, such as Ethernet, OIF CEI-112G, PCI-SIG\u00ae PCIe\u00ae Gen 1 through 6, and insertion loss from few to above 30dB, while maintaining the sub 10ns latency.<\/span><\/p>

\u201cThis 400G LR IP ultra-low latency solution is the culmination of many years of effort and in response to tier-1 customer demands. Current solutions for FEC and PHY have combined latency in 100ns\u00a0range\u00a0and we are pleased to introduce our silicon-proven sub 10ns solution,\u201d said Harry Chan, founder and CEO of eTopus \u201cNow customers developing switches, NIC cards, DPU, re-timers, and active cables can leverage our 400G LR IP solution to slash latency and directly accelerate system performance.\u201d<\/span><\/p>

\u201cThe eTopus 400G LR IP solution with their ultra-low latency PHY aligns well with demand from our customers for integrated\u00a0chiplet\u00a0solutions based on\u00a0OpenFive\u2019s\u00a0Die-to-Die, Ethernet and Interlaken Controllers, particularly in High Performance Computing (HPC) and Data Center accelerator applications.\u201d said Mohit Gupta, SVP and GM, SoC IP at\u00a0OpenFive.<\/span><\/p>

Key Background Facts<\/span><\/b><\/p>

– BER of < 1e-17 is required for data integrity to support customer needs<\/span><\/p>

– For PAM 4 a FEC is mandatory\u00a0and\u00a0\u00a0eTopus\u00a0solution is a combination of SerDes and FEC IP\u00a0 delivering robust post-FEC BER < 1e-17<\/span><\/p>

– Currently just with\u00a0standard\u00a0 RS(544, 514) FEC, latency is 100ns range which for access time dependent solutions limits performance<\/span><\/p>

– eTopus\u00a0ePHY\u00a0SerDes and Ultra Low Latency FEC IP solution easily meets the performance requirement of post-FEC BER <1e-17\u00a0<\/span><\/p>

About eTopus Technology Inc.<\/span><\/b><\/p>

eTopus is the technology leader in high performance, DSP-based, mixed-signal, ultra-high-speed semiconductor interconnect solutions. Our ultra-high-speed SerDes IP is adopted by global Tier-1 players to be used in networking, storage, 5G, and AI applications. eTopus is a VC-backed startup headquartered in Silicon Valley where our innovations and advanced architectures are developed. Our investors include SK Telecom, HK-X, corporate VCs, and cross-border funds. For more information, please visit etopus.com.<\/span><\/p>

About\u00a0OpenFive<\/span><\/b><\/p>

OpenFive, a\u00a0SiFive\u00a0business unit, is focused on custom silicon solutions and differentiated IP. With spec-to-silicon design capabilities, customizable SoC platforms, and differentiated IP for Artificial Intelligence, Cloud\/Datacenter, High Performance Computing PC, Networking, and Storage applications,\u00a0OpenFive\u00a0is uniquely positioned to deliver highly competitive processor agnostic domain-specific SoCs.<\/span><\/p>

The OpenFive IP portfolio includes High-Bandwidth Memory (HBM3\/2E) and low power LPDDR5\/4x memory subsystems; Die-to-Die (D2D) interface IP subsystems for heterogeneous multi-die connectivity including chiplets; low-latency, high-throughput Interlaken interface IP for chip-to-chip connectivity; 400\/800G Ethernet MAC\/PCS subsystems, and USB controller IP.\u00a0 OpenFive offers end-to-end expertise in custom SoC architecture, design implementation, software, silicon validation, and manufacturing to deliver high-quality silicon in advanced nodes down to 5nm. For more information, please visit www.openfive.com.<\/span><\/p>

Company contacts<\/span><\/b><\/p>

Kash Johal VP Sales\u00a0|\u00a0Tel:+1-408-390-8649\u00a0|\u00a0email: Kash.johal@etopus.com<\/a><\/span><\/p><\/div>

Reference: https:\/\/www.einnews.com\/pr_news\/554137793\/etopus-introduces-400g-4x100g-lr-ip-solution-incorporating-new-fec-ephy-with-combined-latency-of-sub-10ns<\/a><\/p>

\u00a0<\/p><\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t

\u5206\u4eab\u8baf\u606f<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t
<\/path><\/svg><\/span><\/a><\/path><\/svg><\/span><\/a><\/path><\/svg><\/span><\/a><\/svg><\/span><\/a><\/div>
<\/div><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t