{"id":6475,"date":"2022-06-21T05:00:36","date_gmt":"2022-06-21T12:00:36","guid":{"rendered":"https:\/\/etopus.com\/?p=6475"},"modified":"2022-06-19T18:51:22","modified_gmt":"2022-06-20T01:51:22","slug":"avery-design-systems-pci-express-vip-enables-etopus-serdes-ip-and-next-generation-asic-and-chiplet-applications-to-achieve-compliance-and-high-speed-connectivity","status":"publish","type":"post","link":"https:\/\/etopus.com\/zh\/avery-design-systems-pci-express-vip-enables-etopus-serdes-ip-and-next-generation-asic-and-chiplet-applications-to-achieve-compliance-and-high-speed-connectivity\/","title":{"rendered":"Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet applications to Achieve Compliance and High-Speed Connectivity"},"content":{"rendered":"
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Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet Applications to Achieve Compliance and High-Speed Connectivity<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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Tewksbury, MA., June 21, 2022<\/span><\/b><\/p>

Avery Design Systems, a leader in functional verification solutions, today announced it <\/span>has been chosen by eTopus as its verification IP solution partner for eTopus PCIe Gen 1-6 and 800G\/400G Ethernet solutions and 112G SerDes IP for next-generation ASIC and Chiplet applications.<\/span>\u00a0<\/span><\/p>

eTopus designs ultra-high speed mixed-signal semiconductor solutions for high-performance computing and data center applications. Its high speed, low latency, low power connectivity IP supports leading-edge PCIe and Ethernet connectivity and uses Avery\u2019s PCI Express Verification IP (VIP) to ensure its IP is compliant prior to silicon validation.<\/span>\u00a0<\/span><\/p>

\u201cAs designs move towards higher speeds, ultra-high speed SerDes IP is essential for leading edge networking, storage, 5G, and AI applications\u201d, said Harry Chan CEO of eTopus.\u00a0 \u201cAvery VIP gives us confidence that our innovations in ADC\/DSP-based physical layer transceiver technology deliver superior bit error rate performance, lower latency and low power consumption while meeting standards compliance.\u201d<\/span>\u00a0<\/span><\/p>

Avery VIP was used to validate the eTopus 7\/6nm modular SerDes\u202fIP optimized for PCIe gen 1 to 6 and 800G SoC & Chiplet\u202fclients. This new 800G solution supports Ethernet standards from 1G to 112G with support for up to 45+ dB long reach applications.<\/span>\u00a0<\/span><\/p>

The Avery PCI Express VIP is a comprehensive verification solution featuring an advanced UVM environment that supports the latest features and capabilities in the high-speed interconnect protocol.<\/span>\u00a0<\/span><\/p>

\u201cWe are pleased to collaborate with eTopus on the introduction of PCIe Gen6 PHY solutions to our mutual customers,\u201d said Chris Browy, VP Sales\/Marketing of Avery Design Systems.\u00a0\u00a0<\/span>\u00a0<\/span><\/p>

Avery is a leader in PCIe VIP and works with its ecosystem partners to ensure a comprehensive and leading-edge IP solution.\u00a0 The Avery SystemVerilog\/UVM VIP solution includes models, protocol checking, compliance testsuites, and Virtual Host QEMU co-simulation \u2013 enabling customers to tackle new PCIe 6.0 design and verification challenges even when no mainstream commercial platforms support the latest standards.\u00a0<\/span>\u00a0<\/span><\/p>

About eTopus Technology Inc.<\/span><\/b>\u202f<\/span>\u00a0<\/span><\/p>

eTopus is an innovator and technology leader in high performance, DSP-based, mixed-signal, ultra-high-speed semiconductor interconnect solutions. Our ultra-high-speed SerDes IP is adopted by global Tier-1 players to be used in networking, storage, 5G, and AI applications. eTopus is a VC-backed startup headquartered in the center of Silicon Valley where our innovations and advanced architectures are developed. Multiple locations are set up globally in USA, Europe and Greater China to provide sales, design and customer support. Our investors include SK Telecom, HK-X, corporate VCs, and cross-border funds. For more information, please visit\u202f<\/span>eTopus.com<\/span><\/a>\u202f<\/span>\u00a0<\/span><\/p>

About Avery Design Systems<\/span><\/b>\u00a0<\/span><\/p>

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential back tracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI\/DSI, I3C, DDR\/LPDDR, HBM, ONFI\/Toggle\/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD\/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information is available at <\/span>www.avery-design.com<\/span><\/a>.<\/span>\u00a0<\/span><\/p>

Compute Express Link and CXL are trademarks of the CXL Consortium<\/span><\/i>\u00a0<\/span><\/p>

PCI Express and PCIe<\/span><\/i>\u00ae are trademarks of PCI-SIG<\/span><\/i>\u00a0<\/span><\/p>

\u00a0<\/span><\/p>

Company contacts:<\/strong><\/p>

Avery Design Systems<\/strong><\/p>

Christopher Browy | Tel: +1-978-851-3627 | email: <\/span>cbrowy@avery-design.com<\/span><\/a><\/p>

Etopus Technologies Inc.<\/strong><\/p>

Kash Johal | VP Sales | Tel:+1-408-390-8649 | email: Kash.johal@etopus.com<\/a><\/p>

Press Contact<\/strong><\/p>

Mike <\/span>Sottak | Tel: +1-650-248-9597 | email:\u00a0<\/span>mike@wiredislandpr.com<\/span><\/span><\/a><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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