eTopus presents innovative SerDes Technology at ISSCC 2021
February 11, 2021
What:
eTopus Technology, a pioneer of ultra-high-speed ADC/DSP-based SerDes for wireline applications, is presenting innovative SerDes architecture that substantially enhances system Bit Error Rate performance and Clock Data Recovery robustness at the 2021 IEEE International Solid-State Circuits Conference (ISSCC).
Read our latest Press Release:
Paper Presentation and live Demonstration:
A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm
Who:
- Mr. Danfeng Xu (co-founder & VP of analog design) – Paper presentation (Full-Presentation is Available Online Now!)
- Dr. Peter Kou (co-founder & CTO) & Mr. Danfeng Xu – Demonstration
When:
Tuesday, February 16, 2021
- 8:30AM – 9:30AM (PST) – Session 8
- 9:02AM – 9:10AM – Paper 8.5 Summary Presentation and Live Q&A session
- 9:30AM – 10:00AM (PST) – Author interview
Friday, February 19, 2021
- 7:00AM – 8:00AM (PST) – Demonstration Session 1
Where:
The 2021 ISSCC event is virtual, and registration for online access can be found here.
More About eTopus:
- View our latest video: eTopus SerDes Technology
We welcome any questions you might have about our technology, and we will partner with you to help your next project.
Best Regards,
Harry Chan
Founder & CEO
